FIGS. 4(a) to 4(d) are cross-sectional side views showing major process steps for producing a semiconductor device according to the prior art. In the figures, reference numeral 1 designates a semi-insulating GaAs substrate. An n type active layer 2 is disposed in the semi-insulating GaAs substrate 1. A gate electrode 3 comprising refractory metal is disposed on the active layer 2. N' type intermediate dopant concentration active layers (hereinafter referred to as "n' layer") 4a (4a') and 4b are disposed adjacent the n type active layer 2. N.sup.+ type high dopant concentration active layers n(hereinafter referred to as "n.sup.+ layer") 8a and 8b are disposed adjacent the n' layer 4a' and the n type active layer 2, respectively. A source electrode 9 and a drain electrode 10 are disposed on the n.sup.+ layers 8a and 8b, respectively. Reference numeral 6 designates photoresist.
The production method will be described.
First of all, as shown in FIG. 4(a), an n type active layer 2 is produced in a semi-insulating GaAs substrate 1 by ion implantation or epitaxial growth. Thereafter, a refractory metal is plated on the entire surface of wafer and patterned by reactive ion etching using photoresist as a mask, thereby to produce a refractory metal gate electrode 3.
Next, as shown in FIG. 4(b), dopant ions are implanted using the refractory metal gate electrode 3 as a mask, whereby n' layers 4a and 4b are produced at both sides of the gate electrode 3.
Next, as shown in FIG. 4(c), photoresist is deposited on the entire surface of substrate and patterned in an asymmetrical configuration with respect to the refractory metal gate electrode 3, and dopant ions are implanted using the patterned photoresist 6 as a mask, whereby n.sup.+ layers 8a and 8b are produced at asymmetrical positions with respect to the gate electrode 3.
After, an annealing process, as shown in FIG. 4(d), a drain electrode 10 is deposited on the n.sup.+ layer 8a at the side where the n' layer 4a' remain and a source electrode 9 is deposited on the n.sup.+ layer 8b at the opposite side of the gate electrode 3 by vapor deposition and lift-off, thereby completing a field effect transistor.
In the above-described production method, however, the ion implantation for producing the n.sup.+ layers 8a and 8b to use the photoresist 6 as a mask, and the distance between the gate electrode 3 and the n.sup.+ layer 8a is determined by the precision of patterning the photoresist. Therefore, in the field effect transistor obtained by the above-described production method, there is a large variation in the gate-drain breakdown voltage and variation in the performance of the transistor. Furthermore, since the distance between the gate electrode 3 and the n.sup.+ layer 8b at the side of source electrode 9 is zero, a sufficient breakdown voltage cannot be obtained.
Another prior art production method will be described.
FIGS. 5(a) to 5(e) are cross-sectional side views showing major process steps for producing a semiconductor device disclosed in Japanese Published Patent Application 63-107071. In the figures reference numeral 21 designates a semiconductor substrate. An active region 22 is disposed on the semiconductor substrate 21. A gate electrode 23 is disposed on the active region 22. A first insulating film 24 (24', 24") is disposed on the active region 22. Reference numeral 25 designates photoresist. Reference numeral 26 (26') designates a second insulating film. Reference numeral 27 designates a contact region.
The production method will be described.
First of all, as shown in FIG. 5(a), an active region 22 and a gate 23 are produced on the GaAs substrate 21, and thereafter, a first insulating film 24 having a thickness t.sub.1 is deposited thereon. Thereafter, photoresist is deposited on the entire surface, exposed, and developed thereby to obtain a photoresist 25 having a configuration as shown in FIG. 5(b). Subsequently, as shown in FIG. 5(c), a portion of the oxide film 24 is removed by a dilute solution of hydro-fluoric acid using the photoresist 25 as a mask. Thereafter, as shown in FIG. 5(d), after removing the photoresist 25, a second insulating film 26 having thickness t.sub.2 is deposited on the entire surface. Then, as shown in FIG. 5(e), the entire surface is selectively etched to produce asymmetric configuration side walls 24" and 26' at respective sides of the gate 23', contact regions 27 are produced by ion beam implantation with using the side walls 24', 26' and the gate 23 as a mask. The contact regions 27 are asymmetric with respect to the gate 23 yet self-aligning due to the difference between the thickness of the side wall 24" and that of the side wall 26'.
In such field effect transistor, a predetermined distances are provided between the gate 23 and the respective contact layers 27, and therefore, high gate-drain breakdown voltage can be obtained and current leakage between the gate and the source side contact layer 27 is prevented.
In the prior art production method of a semiconductor device, however, the following problems arise in the actual production steps.
There is no anisotropicity in the wet etching of removing the insulating film 24 at the gate side using the photoresist 25 as a mask, as shown in FIG. 6. The photoresist 25 is attached at the side, removing some of the first insulating film 24' below the photoresist 25. Even if this etching is dry etching, the etching selectivity of the first insulating film 24 relative to the gate 23 and GaAs substrate 2 is about 1:10, and it is difficult to remove only the first insulating film 24 by the etching. Therefore, as shown in FIG. 7, the surface of substrate and the side wall of gate 23 are also etched and damaged at the same time, causing arising variations in the gate length and reductions in the thickness of the active layer 22 in the substrate 21. This results in variations and deteriorations in the FET performance.
Secondly, in the process of producing side wall insulating films 24" and 26' which are asymmetrical with respect to the gate 23 by reactive ion etching (RIE), the film thicknesses, and t.sub.2 of the insulating films are different to the left and right of the gate 23 as shown in FIG. 8(a), and the time is required for equal etching is differentiate. Therefore, as shown in FIG. 8(b), when the insulating film 26' is produced at the side wall of the gate 23, the first insulating film 24' still remains on the active layer 22 and on a portion of the gate 23. Accordingly, if the insulating film 24' is further etched until a side wall insulating film 24" comprising the first insulating film 24' of a desired configuration is produced, the side wall insulating film 26' comprising the second insulating film which has already been produced is almost totally removed. Thus, a desired side wall insulating film having an asymmetrical configuration will not be obtained, thereby increasing the variation of the gate-drain breakdown voltage. Furthermore, there are current leakages between the gate and source region, thereby deteriorating the FET performance. Furthermore, in this process, the active layer 22 and the gate 23 at the side where the side wall insulating film 26' is produced are damaged by etching, thereby deteriorating the FET performance to a great extent.